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16 x 16 PARALLEL CMOS MULTIPLIERS
Integrated Device Technology, Inc.
IDT7216L IDT7217L
FEATURES:
* * * * * * 16 x 16 parallel multiplier with double precision product 16ns clocked multiply time Low power consumption: 120mA Produced with advanced submicron CMOS high performance technology IDT7216L is pin- and function compatible with TRW MPY016H/K and AMD Am29516 IDT7217L requires a single clock with register enables making it pin- and function compatible with AMD Am29517 Configured for easy array expansion User-controlled option for transparent output register mode Round control for rounding the MSP Input and output directly TTL-compatible Three-state output Available in Top Braze, DIP, PLCC, Flatpack and Pin Grid Array Military product compliant to MIL-STD-883, Class B Standard Military Drawing #5962-86873 is listed on this function for IDT7216 and Standard Military Drawing #5962-87686 is listed for this function for IDT7217. Speeds available: Commercial: L16/20/25/35/45/55/65 Military: L20/25/30/40/55/65/75
IDT7216 RND YM Y15-0/P15-0
16
REGISTER YREGISTER
DESCRIPTION:
The IDT7216/IDT7217 are high-speed, low-power 16 x 16-bit multipliers ideal for fast, real time digital signal processing applications. Utilization of a modified Booths algorithm and IDT's high-performance, submicron CMOS technology, has achieved speeds comparable to bipolar (20ns max.), at 1/10 the power consumption. The IDT7216/IDT7217 are ideal for applications requiring high-speed multiplication such as fast Fourier transform analysis, digital filtering, graphic display systems, speech synthesis and recognition and in any system requirement where multiplication speeds of a mini/microcomputer are inadequate. All input registers, as well as LSP and MSP output registers, use the same positive edge-triggered D-type flip-flop. In the IDT7216, there are independent clocks (CLKX, CLKY, CLKM, CLKL) associated with each of these registers. The IDT7217 has only a single clock input (CLK) and three register enables. ENX and ENY control the two input registers, while ENP controls the entire product. The IDT7216/IDT7217 offer additional flexibility with the FA control and MSPSEL functions. The FA control formats the output for two's complement by shifting the MSP up one bit and then repeating the sign bit in the MSB of the LSP. The
* * * * * * * *
*
FUNCTIONAL BLOCK DIAGRAMS
XM X15-0
16
XREGISTER
XM X15-0
16
XREGISTER
IDT7217 RND
REGISTER
YM Y15-0/P15-0
16
YREGISTER
CLKY CLKX OEL
CLK ENX ENY MULTIPLIER ARRAY MULTIPLIER ARRAY
OEL
FA FT CLKM CLKL MSPSEL OEP
FORMAT ADJUST MSP LSP REGISTER REGISTER 16 16
FA FT ENP
FORMAT ADJUST MSP LSP REGISTER REGISTER 16 16
MULTIPLEXER
MSPSEL OEP
MULTIPLEXER
PRODUCT
16
2580 drw 01
PRODUCT
16
2580 drw 02
MSPOUT (P31 - P16)
The IDT Logo is a registered trademark of Integrated Device Technology, Inc.
MSPOUT (P31 - P16)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1995 Integrated Device Technology, Inc.
AUGUST 1995
DSC-2023/6
11.3
1
IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DESCRIPTION (Cont'd.) MSPSEL low selects the MSP to be available at the product
output port, while a high selects the LSP to be available. Keeping this pin low will ensure compatibility with the TRW MPY016H.
The IDT7216/IDT7217 multipliers are manufactured in compliance with the latest revision of MIL-STD-883, Class B, making them ideally suited to applications demanding the highest level of performance and reliability.
PIN CONFIGURATIONS
IDT7216 IDT7217
X4 X3 X2 X1 X0 OEL CLKL CLKY P0, Y0 P1, Y1 P2, Y2 P3, Y3 P4, Y4 P5, Y5 P6, Y6 P7, Y7 P8, Y8 P9, Y9 P10, Y10 P11, Y11 P12, Y12 P13, Y13 P14, Y14 P15, Y15 P0, P16 P1, P17 P2, P18 P3, P19 P4, P20 P5, P21 P6, P22 P7, P23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 C64-2 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 CLKX RND XM YM VCC VCC GND GND MSPSEL FT FA OEP CLKM P15, P31 P14, P30 P13, P29 P12, P28 P11, P27 P10, P26 P9, P25 P8, P24
2580 drw 03
X4 X3 X2 X1 X0 OEL CLK ENY P0, Y0 P1, Y1 P2, Y2 P3, Y3 P4, Y4 P5, Y5 P6, Y6 P7, Y7 P8, Y8 P9, Y9 P10, Y10 P11, Y11 P12, Y12 P13, Y13 P14, Y14 P15, Y15 P0, P16 P1, P17 P2, P18 P3, P19 P4, P20 P5, P21 P6, P22 P7, P23
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 C64-2 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
X5 X6 X7 X8 X9 X10 X11 X12 X13 X14 X15 ENX RND XM YM VCC VCC GND GND MSPSEL FT FA OEP ENP P15, P31 P14, P30 P13, P29 P12, P28 P11, P27 P10, P26 P9, P25 P8, P24
2580 drw 04
64-PIN DIP TOP VIEW
64-PIN DIP TOP VIEW
11.3
2
IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (Cont'd.)
IDT7216/IDT7217
11 10 09 08 07 06 05 04 03 02 01 Pin 1 Designator A X11 X9 X7 X5 X3 X1 OEL
CLKY or ENY*
NC X12 X10 X8 X6 X4 X2 X0
CLKL or CLK*
X13 X14
X15
CLKX or ENX*
RND XM
YM
VCC GND
FT FA
OEP
CLKM or ENP*
VCC GND MSPSEL
NC P31, P15 P29, P13 P27, P11 P25, P9 P23, P7 P21, P5 P19, P3 P17, P1
P30, P14 P28, P12 P26, P10 G68-2 P24, P8 P22, P6 P20, P4 P18, P2 Y2, P2 Y3, P3 C Y4, P4 Y5, P5 D Y6, P6 Y7, P7 E Y8, P8 Y9, P9 F Y10, P10 Y11, P11 G Y12, P12 Y13, P13 H Y14, P14 Y15, P15 J P16, P0 NC K
NC
Y0, P0 Y1, P1 B
L
*Pin designation for IDT7217 PGA TOP VIEW
2580 drw 05
11.3
3
IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS (Cont'd.)
IDT7216
OEP FA FT MSPSEL GND GND VCC VCC YM XM RND CLKX X15 X14 X13
IDT7217
ENP OEP FA FT MSPSEL GND GND VCC VCC YM XM RND ENX X15 X14 X13
64636261 605958575655 545352 515049
64636261 605958575655 545352 515049
P15, P31 P14, P30 P13, P29 P12, P28 P11, P27 P10, P26 P9, P25 P8, P24 P7, P23 P6, P22 P5, P21 P4, P20 P3, P19 P2, P18 P1, P17 P0, P16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
F64-1
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 OEL CLKL CLKY
P15, P14, P13, P12, P11, P10, P9, P8, P7, P6, P5, P4, P3, P2, P1, P0,
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
F64-1
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 OEL CLK ENY
17181920 212223242526 272829 303132
17181920 212223242526 272829 303132
P15, Y15 P14, Y14 P13, Y13 P12, Y12 P11, Y11 P10, Y10 P9, Y9 P8, Y8 P7, Y7 P6, Y6 P5, Y5 P4, Y4 P3, Y3 P2, Y2 P1, Y1 P0, Y0
2580 drw 06
P15, Y15 P14, Y14 P13, Y13 P12, Y12 P11, Y11 P10, Y10 P9, Y9 P8, Y8 P7, Y7 P6, Y6 P5, Y5 P4, Y4 P3, Y3 P2, Y2 P1, Y1 P0, Y0
2580 drw 07
64-LEAD FLATPACK TOP VIEW
64-LEAD FLATPACK TOP VIEW
NC X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 OEL CLKL CLKY
60 59 58 5756 5554 53 5251 50 4948 47 46 45 44
60 59 58 5756 5554 53 5251 50 4948 47 46 45 44
43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
X13 61 X14 62 X15 63 CLKX 64 RND 65 XM 66 YM 67 VCC 68 VCC 1 GND 2 GND 3 MSPSEL 4 FT 5 FA 6 OEP 7 CLKM 8 NC 9
J68-1 L68-1, L68-1
NC P0, Y0 P1, Y1 P2, Y2 P3, Y3 P4, Y4 P5, Y5 P6, Y6 P7, Y7 P8, Y8 P9, Y9 P10, Y10 P11, Y11 P12, Y12 P13, Y13 P14, Y14 P15, Y15
X13 61 X14 62 X15 63 ENX 64 RND 65 XM 66 YM 67 VCC68 VCC 1 GND 2 GND 3 MSPSEL 4 FT 5 FA 6 OEP 7 ENP 8 NC 9
NC X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0 OEL CLK ENY
IDT7216
IDT7217
L68-1, L68-1 J68-1
43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
NC P0, Y0 P1, Y1 P2, Y2 P3, Y3 P4, Y4 P5, Y5 P6, Y6 P7, Y7 P8, Y8 P9, Y9 P10, Y10 P11, Y11 P12, Y12 P13, Y13 P14, Y14 P15, Y15
10 1112 13 14 1516 17 1819 20 212223 24 25 26
P15, P31 P14, P30 P13, P29 P12, P28 P11, P27 P10, P26 P9, P25 P8, P24 P7, P23 P6, P22 P5, P21 P4, P20 P3, P19 P2, P18 P1, P17 P0, P16 NC
10 1112 13 14 1516 17 1819 20 2122 23 24 25 26
P15, P31 P14, P30 P13, P29 P12, P28 P11, P27 P10, P26 P9, P25 P8, P24 P7, P23 P6, P22 P5, P21 P4, P20 P3, P19 P2, P18 P1, P17 P0, P16 NC
2580 drw 08
2580 drw 09
PLCC TOP VIEW
PLCC TOP VIEW
11.3
4
IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN DESCRIPTIONS
Pin Name X0 - X15 Y0 - Y15/ P0 - P15 P16 - P31 I/O I I/O O I I I I Data Inputs Y0 - Y15 are data inputs P0 - P15 are LSP register output, enabled when OEL = 0 Data Output (LSP or MSP) Output enable control for LSP (least significant product). When low enables P0 - P15. When high P0 - P15 tristated. Output enable control for MSP (most significant product). When low enables P16 - P31. When high P16 P31 tristated. Mode control for each data word. Low designates unsigned data input and high designates two's complement. "Round" control for rounding of MSP. When high, 1 is added to the most significant bit of LSP. This signal is affected by the state of FA pin. When FA = 1 and RND = 1, 1 is added to the 2-15 bit (P15). When RND = 1 and FA = 0, 1 is added to the 2 -16 bit (P14). The RND input is registered. It is clocked on the rising edge of the logical OR of CLKX and CLKY in the 7216 and on the rising edge of CLK in the 7217. Rounding always occurs in the positive direction which may introduce a systematic bias. When low, MSP is output on P16 - P31 lines. When high, LSP is output on P16 - P31. Format adjust control. When high, a full 32 bit product is selected. When low, a left shifted 31 bit product is selected with the sign bit replicated in the LSP. FA is normally high, except for certain fractional two's complement applications (see multiplier input / output formats). Flow through control. When high, both MSP and LSP registers are by-passed. 7217 X, Y, RND, LSP and MSP register clock input. 7216 X register clock input. Also clocks RND register. 7216 Y register clock input. Also clocks RND register. 7216 LSP register clock input. 7216 MSP register clock input. 7217 X register clock enable. Also enables RND register clock. 7217 Y register clock enable. Also enables RND register clock. Description
OEL OEP
XM, YM RND
MSPSEL
FA
I I
FT CLK CLKX CLKY CLKL CLKM
I I I I I I I I
ENX ENY
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC VTERM Rating Power Supply Voltage Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial -0.5 to +7.0 VCC + 0.5 Military -0.5 to +7.0 VCC + 0.5 Unit V V C C C mA
CAPACITANCE (TA = +25C, f = 1.0 MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 10 12 Unit pF pF
NOTE: 2580 tbl 04 1. This parameter is measured at characterization and not tested.
TA TBIAS TSTG IOUT
0 to +70 -55 to +125 -55 to +125 50
-55 to +125 -65 to +135 -65 to +150 50
NOTE: 2580 tbl 01 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
11.3
5
EL
IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5.0V 10%, TA = 0C to +70C; Military: VCC = 5V 10%, TA = -55C to +125C)
Commercial Symbol VIH VIL |ILI| |ILO| ICC ICCQ1 ICCQ2 Parameter Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Operating Power Supply Current Quiescent Power Supply Current Quiescent Power Supply Current Test Conditions(1) Min. 2.0 -- -- -- -- -- -- -- 2.4 -- -20 Typ.(1) -- -- -- -- 40 20 4 -- -- -- -- Max. -- 0.8 10 10 80 40 20 4 -- 0.4 -120 Min. 2.0 -- -- -- -- -- -- -- 2.4 -- -20 Guaranteed Logic High Level Guaranteed Logic Low Level VCC = Max., VIN = 0 to VCC VCC = Max., OE = 2.0V VOUT = 0 to VCC VCC = Max., Outputs Disabled f = 10MHz(2) VIN VIH, VIN VIL VIN VCC - 0.2V, VIN 0.2V VCC = Max., Outputs Disabled VCC = Min., IOH = -2.0mA VCC = Min., IOL = 8mA VCC = Max., VO = GND Military Typ.(1) -- -- -- -- 40 20 4 -- -- -- -- Max. -- 0.8 10 10 100 50 25 6 -- 0.4 -120 Unit V V A A mA mA mA mA/ MHz V V mA
ICC/f (2,3) Increase in Power Supply Current VOH Output HIGH Voltage VOL(4) IOS Output LOW Voltage Output Short Circuit Current
NOTES: 2580 tbl 03 1. Typical implies VCC = 5V and TA = +25C. 2. ICC is measured at 10MHz and VIN = 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range: ICC = 80+ 4(f -10)mA; for the military range, ICC = 100 + 6(f -10). f = operating frequency in MHz, f = 1/tMUC for IDT7216 and f = 1/tMC for IDT7217. 3. For frequencies greater than 10MHz, guaranteed by design, not production tested. 4. IOL = 4mA for tMC >65ns.
11.3
6
IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS COMMERCIAL (VCC = 5V 10%, TA = 0 to +70C)
Symbol tMUC tMC tS tH tPWH tPWL tPDSEL tPDP tPDY tENA tDIS tS tH tHCL Parameter Unclocked Multiply Clocked Multiply Time(4) X, Y, RND Set-up Time X, Y, RND Hold Time Clock Pulse Width High Clock Pulse Width Low MSPSEL to Product Out(4) Output Clock to P (4) Output Clock to Y (4) 3-State Enable Time 3-State Disable Time(2) Clock Enable Set-up Time (IDT7217 only) Clock Enable Hold Time (IDT7217 only) Clock Low Hold Time CLKXY Relative to CLKML (IDT7216 only)(1,3) Time(4) 7216L16 (5) 7217L16 Min. Max. 2 2 10 1 7 7 2 2 2 -- -- 9 0 0 25 16 -- -- -- -- 15 15 15 15 15 -- -- -- 7216L20 7217L20 Min. Max. 2 2 11 1 9 9 2 2 2 -- -- 10 0 0 30 20 -- -- -- -- 18 18 18 18 18 -- -- -- 7216L25 7217L25 Min. Max. 2 2 12 2 10 10 2 2 2 -- -- 10 2 0 38 25 -- -- -- -- 20 20 20 20 20 -- -- -- 7216L35 7217L35 Min. Max. 2 2 12 3 10 10 2 2 2 -- -- 10 3 0 55 35 -- -- -- -- 25 25 25 25 22 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol tMUC tMC tS tH tPWH tPWL tPDSEL tPDP tPDY tENA tDIS tS tH tHCL
Parameter Unclocked Multiply Time(4) Clocked Multiply Time(4) X, Y, RND Set-up Time X, Y, RND Hold Time Clock Pulse Width High Clock Pulse Width Low MSPSEL to Product Out(4) Output Clock to P (4) Output Clock to Y (4) 3-State Enable Time 3-State Disable Time(2) Clock Enable Set-up Time (IDT7217 only) Clock Enable Hold Time (IDT7217 only) Clock Low Hold Time CLKXY Relative to CLKML (IDT7216 only) (1,3)
7216L45 7217L45 Min. Max. 2 2 15 3 15 15 2 2 2 -- -- 10 3 0 65 45 -- -- -- -- 25 25 25 25 22 -- -- --
7216L55 7217L55 Min. Max. 2 2 20 3 15 20 2 2 2 -- -- 10 3 0 75 55 -- -- -- -- 25 30 30 30 25 -- -- --
7216L65 7217L65 Min. Max. 2 2 20 3 15 20 2 2 2 -- -- 10 3 0 85 65 -- -- -- -- 30 30 30 35 25 -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 2580 tbl 06 1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been clocked. 2. Transition is measured 500mV from steady state voltage. 3. Guaranteed by design, not production tested. 4. Minimum propagation delay times are guaranteed, not production tested. 5. This speed is available in PGA and PLCC packages only.
11.3
7
IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS MILITARY (VCC = 5V 10%, TA = -55 to +125C)
Symbol tMUC tMC tS tH tPWH tPWL tPDSEL tPDP tPDY tENA tDIS tS tH tHCL Parameter Unclocked Multiply Clocked Multiply Time(4) X, Y, RND Set-up Time X, Y, RND Hold Time Clock Pulse Width High Clock Pulse Width Low MSPSEL to Product Out(4) Output Clock to P (4) Output Clock to Y (4) 3-State Enable Time 3-State Disable Time(2) Clock Enable Set-up Time (IDT7217 only) Clock Enable Hold Time (IDT7217 only) Clock Low Hold Time CLKXY Relative to CLKML (IDT7216 only)(1,3) Time(4) 7216L20 (5) 7217L20 Min. Max. 2 2 11 1 9 9 2 2 2 -- -- 10 0 0 30 30 -- -- -- -- 18 18 18 18 20 -- -- -- 7216L25 7217L25 Min. Max. 2 2 12 2 10 10 2 2 2 -- -- 10 2 0 38 25 -- -- -- -- 20 20 20 20 22 -- -- -- 7216L30 7217L30 Min. Max. 2 2 12 2 10 10 2 2 2 -- -- 10 2 0 43 30 -- -- -- -- 20 20 20 20 22 -- -- -- 7216L40 7217L40 Min. Max. 2 2 15 3 15 15 2 2 2 -- -- 12 3 0 60 40 -- -- -- -- 25 25 25 25 25 -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Symbol tMUC tMC tS tH tPWH tPWL tPDSEL tPDP tPDY tENA tDIS tS tH tHCL
Parameter Unclocked Multiply Clocked Multiply Time(4) X, Y, RND Set-up Time X, Y, RND Hold Time Clock Pulse Width High Clock Pulse Width Low MSPSEL to Product Out(4) Output Clock to P (4) Output Clock to Y (4) 3-State Enable Time 3-State Disable Time(2) Clock Enable Set-up Time (IDT7217 only) Clock Enable Hold Time (IDT7217 only) Clock Low Hold Time CLKXY Relative to CLKML (IDT7216 only) (1,3) Time(4)
7216L55 7217L55 Min. Max. 2 2 20 3 15 15 2 2 2 -- -- 15 3 0 75 55 -- -- -- -- 30 30 30 25 25 -- -- --
7216L65 7217L65 Min. Max. 2 2 25 3 15 15 2 2 2 -- -- 15 3 0 85 65 -- -- -- -- 35 30 30 35 25 -- -- --
7216L75 7217L75 Min. Max. 2 2 25 3 15 15 2 2 2 -- -- 15 3 0 95 75 -- -- -- -- 35 35 35 40 25 -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
NOTES: 2580 tbl 07 1. To ensure that the correct product is entered in the output registers, new data may not be entered into the registers before the output registers have been clocked. 2. Transition is measured 500mV from steady state voltage. 3. Guaranteed by design, not production tested. 4. Minimum propagation delay times are guaranteed, not production tested. 5. This speed is available in PGA and Flatpack packages only.
11.3
8
IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tPWH CLKX CLKY INPUT X1, Y1, RND tMC CLKM CLKL
tHCL
tS
tH
tPWL
tPDY OUTPUT Y
CLKM CLKL tPDSEL MSPSEL tPDP OUTPUT P tMUC
Figure 4. IDT7216 Timing Diagram
2580 drw 13
tPWH CLK tS ENX ENY tS X1, Y1, RND tS ENP tMC OUTPUT Y tPDSEL MSPSEL tPDP OUTPUT P tMUC
Figure 5. IDT7217 Timing Diagram
2580 drw 14
tH
tPWL
tH
tH
tPDY
11.3
9
BINARY POINT
X15 X14 X13 X12 X11 X10 X9 X8 X6 X5 X4 X3 X1 X0
X7
X2
SIGNAL DIGITAL VALUE SIGNAL DIGITAL VALUE
P8 P7 P6 P4 P2 P5 P3 P1 P0
-2 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y1 Y0 Y2
0
2
-1
2
-2
2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2-10 2-11 2 -12 2 -13 2 -14 2 -15
X
Y15 Y14 Y13 Y12 Y11 Y10
-2
0
2
-1
2
-2
2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2-10 2-11 2 -12 2 -13 2 -14 2 -15
IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS
*= MSP LSP
P9 P8 P7 P6 P4 P5 P3 P2
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9
SIGNAL DIGITAL VALUE
-2
0
2
-1
2
-2
2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2-10 2-11 2 -12 2 -13 2 -14 2 -15 -2 0 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2-24 2-25 2-26 2 -27 2 -28 2 -29 2 -30
FA = 0
P1 P0
= MSP
Figure 6. Fractional Two's Complement Notation
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10
SIGNAL DIGITAL VALUE
-2
1
2
0
2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2-10 2-11 2 -12 2 -13 2 -14 2 -15 2 -16 2 -17 2 -18 2 -19 2 -20 2-21 2 -22 2 -23 2-24 2 -25 2-26 2 -27 2 -28 2 -29 2 -30
LSP
FA = 1
2580 drw 16
11.3
BINARY POINT
X15 X14 X13 X12 X11 X10 X7 2 Y7 2
-9 -11 -15 2-12 2-13 2-14 2 2-16 2-10 2 -9 -11 -15 2-12 2-13 2-14 2 2-16 2-10 2
X9 2 Y8 Y6 Y2 Y1 Y0 2
-8 -8
X8 X6 X2 X1 X0
X5
X4
X3
SIGNAL DIGITAL VALUE SIGNAL DIGITAL VALUE
P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
2-1 2-2 Y5 Y4 Y3
2
-3
2-4
2-5 2-6
2-7
X
Y15 Y14 Y13 Y12 Y11 Y10
Y9
2-1 2-2
2
-3
2-4
2-5 2-6
2-7
=
2
-8
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 2
-9
SIGNAL DIGITAL VALUE LSP
-2
-1
2
-2
2
-3
2-4
2-5
2
-6
2-7
-11 -24 -26 -27 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2 2-10 2 2-25 2 2-28 2-29 2-30 2-31 2-32 2
MSP
Figure 7. Fractional Unsigned Magnitude Notation
FA = 1
MANDATORY
2580 drw17
MILITARY AND COMMERCIAL TEMPERATURE RANGES
10
BINARY POINT
X15 X14 X13 X12 X11 X10 X8 X6 X4
X9
X7
X5
X3
X2
X1 X0
-2 0 2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2-10 2-11 2 -12 2 -13 2 -14 2 -15 Y9 Y7 Y5 Y3 Y0 Y8 Y6 Y4 Y2 Y1
SIGNAL (TWO'S COMPLEMENT) DIGITAL VALUE
X
Y15 Y14 Y13 Y12 Y11 Y10
2 -1 2 -2 2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2-10 2-11 2 -12 2 -13 2-14 2 -15 2 -16 P9 P4 P2 P8 P7 P6 P5 P3 P1
SIGNAL (UNSIGNED MAGNITUDE) DIGITAL VALUE
P0
IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS
= MSP
Figure 8. Fractional Mixed Mode Notation
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10
SIGNAL
-2
0
2
-1
2
-2
2 -3 2 -4 2 -5 2 -6 2 -7 2 -8 2 -9 2-10 2-11 2 -12 2 -13 2 -14 2 -15 2 -16 2 -17 2 -18 2 -19 2 -20 2 -21 2 -22 2 -23 2-24 2-25 2-26 2 -27 2 -28 2 -29 2 -30 2 -31 DIGITAL VALUE
LSP
FA = 1
MANDATORY
2580 drw 18
BINARY POINT
11.3
X15 X14 X13 X12 X11 X10
14 13 11 15 210 -2 2 2 212 2
X9 2
9
X8 2 Y9
8
X7 27 Y8 2 P9
8
X6 X5 X4 26 Y7 27 P8 P7 2
5
X3 24 Y6 Y5 Y4 26 P6 2
5
X2 23 Y3 24 P5 P4 22 Y2 23 2 P3
2
X1 X0 21 Y1 21 P2 P1 2
0
SIGNAL DIGITAL VALUE
Y0 2
0
X
Y15 Y14 Y13 Y12 Y11 Y10
SIGNAL DIGITAL VALUE
P0 2
12
14 13 11 2 10 2 9 -215 2 2 2 12 2
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 223 2 2
22 21 2 20
SIGNAL
211 2
10
*=
219 218 217 216 215 -230 214 213 2
9
-2
30
2
29
228 2
27
226 225
224
28
27
26
25
2
4
2
3
22
2
1
2
0
DIGITAL VALUE LSP
P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
MSP
FA = 0
SIGNAL
=
224 2 2 2 223 219
22 21 20
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 2
18
-2
31
230 2
29
228 227 226 225
217
216 215
214 213
2
12
211 2
10
2
9
28
27
26
25
2
4
2
3
22
2
1
2
0
DIGITAL VALUE LSP
MSP
Figure 9. Integer Two's Complement Notation
FA = 1
2580 drw 19
MILITARY AND COMMERCIAL TEMPERATURE RANGES
11
* In this format an overflow occurs in the attempted multiplication of the two's complement number 1,000 . . . 0 with 1,000.0 yielding an erroneous 30 product of -1 in the fraction case and -2 in the integer case.
BINARY POINT
X15 X14 X13 X12 X11 X10 X8 28 2 2 Y5 2 P5 2
5 5 7
X9 X3 2 2 Y2 2 P2 2
2 2 3 2
X7 26 Y6 Y4 24 2 P3 2
3 3 5
X6 X5 X4 24 Y3 21 P1 21 Y1 Y0 20 P0 20 21 20
X2
X1 X0
SIGNAL DIGITAL VALUE SIGNAL DIGITAL VALUE SIGNAL DIGITAL VALUE
15 2
2 Y9 Y8 28 2 P7 27 2
6 7
14
213 2 Y7 26 P6 24 P4 2
212
11
10
29
X
215 2 14 2 13 2 12 2 11 2 10 P9 P8 2
8
Y15 Y14 Y13 Y12 Y11 Y10 29
IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 224 2 2 2 2
23 22
231 230
2
29
2
28
227 226
2
25
221
20 2
219 218
217
216 215
214 213
212
211
10
9
MSB
Figure 10. Integer Unsigned Magnitude Notation
LSP
FA = 1
MANDATORY
2580 drw 20
11.3
BINARY POINT
X15 X14 X13 X12 X11 X10 -215 2 14 2 13 2 12 2 11 2 10 Y15 Y14 Y13 Y12 Y11 Y10
15 2
X9 29 Y9
X8 28 Y8
X7 2
7
X6 26 Y7 Y6
X5 2
5
X4 24 Y5 Y4
X3 2
3
X2 2 Y3
2
X1 21 Y2
X0 20 Y1 Y0
SIGNAL (TWO'S COMPLEMENT) DIGITAL VALUE
X
2
14
213
212
2
11
2
10
29
28 P8 2
8
2
7
26 P7 27 P6 2
6
2
5
24 P5 2
5
2 P4 24
3
2 P3 2
3
2
21 P2 2
2
20 P1 21 P0 20
SIGNAL (UNSIGNED MAGNITUDE) DIGITAL VALUE SIGNAL DIGITAL VALUE LSP
P31 P30 P29 P28 P27 P26 P25 P24 P23 P22 P21 P20 P19 P18 P17 P16 P15 P14 P13 P12 P11 P10 P9 2 19 218 2 17 2 16 2 15 2 14 2 13 2 12 2 11 2 10 2 9
-2
31
2 30 2 29 2 28 2 27 2 26 2 25 2 24 2 23 2 22 221 220
MSB
Figure 11. Integer Mixed Mode Notation
FA = 1
MANDATORY
2580 drw 21
MILITARY AND COMMERCIAL TEMPERATURE RANGES
12
IDT7216L, IDT7217L 16 x 16 PARALLEL CMOS MULTIPLIERS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
VCC 500 Pulse Generator VIN D.U.T. 50pF RT CL 500 V OUT
Input Pulse Levels
7.0V
GND to 3.0V 3ns 1.5V 1.5V See Figure 1
2580 tbl 08
Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load
SWITCH POSITION
Test Disable Low Enable Low All Other Tests Switch Closed Open
Figure 12. AC Test Load Circuit DEFINITIONS: 2580 tbl 09 CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
VCC ESD PROTECTION IIH INPUTS IIL R IOL
IOH OUTPUTS
Figure 13. Input Interface Circuit
Figure 14. Output Interface Circuit
ORDERING INFORMATION
IDT XXXX Device Type X Power X Speed X Package X Process/ Temperature Range Blank B Commercial (0C to +70C) Military (-55C to +125C) Compliant to MIL-STD-883, Class B
C J F G 16 20 25 35 45 55 65 L 7216 7217
Topbraze DIP Plastic Leaded Chip Carrier Flatpack Pin Grid Array 20 25 30 Commercial (tMC) 40 55 65 75 Low Power 16 x 16 Multiplier
2580 drw 22
Military (tMC)
11.3
13

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